55 thoughts on “UVM Tutorial for Candy Lovers – 7. Virtual Sequence”

1. Hi,

   I have a basic doubt related to raising an objection.

   In many examples i found the objection is raised from inside the sequences, or may be some other components.
   Here, in this example, the objection is raised from the testcase.

   How to decide on the point of raising an objection? What all factors incfluence that? Does it make any difference if i raise an objection from a sequence or from a testcase?

   Reply

   1. An objection should be raised if a component or a sequence does not want to move on to the next phase. For example, the jelly_bean_recipe_test wanted to run for 100 ns, so it raised an objection. If a test pushes 100 requests to a request queue, but the test does not know when these requests finish, the request queue should also raise an objection as long as there is a request in the queue. A scoreboard is another candidate to raise an objection.

      Reply

2. Hi Keisuke,

   I found the post is very helpful for me to understand the uvm. I wonder what is the reason that seq1.start needs to provide parent_sequence, but the gift_box example, sequence of sequences does not need parent_sequence.

   Thanks.

   Reply

   1. The jb_seq1 and jb_seq2 are children of the jelly_bean_recipe_virtual_sequence. If the parent_sequence is provided, the parent_sequence‘s pre_do, mid_do, and post_do methods will be called during the execution of the jb_seq1 and jb_seq2.
      Similarly the gift_boxed_jelly_beans_sequence should have provided the parent_sequence when it called jb_seq.start(). I have corrected the example (the line 15 of gift_boxed_jelly_beans_sequence of this article). Thank you for pointing this out.

      Reply

      1. Hi Keisuke,

         Thanks for your update and explanation. It helps me a lot.

         Reply

         1. I am glad to hear that it is useful.

            Reply

3. Hi Keisuke,

   I am new to virtual_seq. In line 1,
   class jelly_bean_recipe_virtual_sequence extends uvm_sequence#( uvm_sequence_item );

   Since virtual_seq does not work with a driver, why do we need uvm_sequence_item? Is it ok to leave it out.
   class jelly_bean_recipe_virtual_sequence extends uvm_sequence;

   Many thanks.

   Reply

   1. Hi Loren,

      As you mentioned, the type parameter of the uvm_sequence# class is not important here. Since the default type is uvm_sequence_item, you can omit the type.

      Reply

4. Hi Keisuke,

   I have a few questions related to sequence. Can you give me some pointer?
   1. This is the problem. I want to test multiplexer interface in DUT. Each output is connection to a 4 deep FIFO. I don’t want to interface to be idle when any of the FIFO is full. The driver will drive 2bit control bit, and 8-bit data. (this is my sequence item) So I want to use 4 sema to keep track of each fifo assuming the I can put token back to sema when I drain out 1 entry from the fifo.

   1. should I pass the sema to a sequence, and In the body(), I try_put sema to randomize the 2bit control bit?
   2. should I use the sema info in the driver?
   What is the most practical way to implement this?

   2. When I compare the syntax of seq, and virtual seq, they are very similar except:
   a. virtual seq is not associated with a user-defined sequence_item.
   b. virtual seq has sequencer for each of the sub-seq.
   Are these the only different?

   Many thanks.

   Reply

   1. Hi Loren,

      1. I’m afraid I might not understand your DUT well, but I would probably put control bit info in a transaction so that I can fully control the driver behavior.
      2. Yes, a virtual sequence is nothing but a sequence. The only difference is that it co-ordinates multiple sequences on different sequencers.

      Reply

5. Mr. Shimizu,
   Thanks for the wonderful explanation. Could also explain about Virtual Sequencers ? As per your explanation, I understood that Virtual Sequences co-ordinates multiple sequences on different sequencers. how does it differ from Virtual Sequencer.
   Thanks.

   Reply

   1. A virtual sequencer also has the handles to the coordinated sequencers, and you can create a virtual sequence that runs on the virtual sequencer. However, this approach adds an unnecessary component (virtual sequencer) to the verification environment and it negatively affects the reusability of the environment. I would recommend not to use the virtual sequencer.

      Reply

6. Hi,
   I youe code you have not used virtual sequencer my question is

   Why do we need virtual sequencer when the same can be done with the above example.

   What are the disadvantage of using the above example.

   Reply

   1. A virtual sequencer is not needed. Please see my comment above.

      Reply

7. I’m new to UVM, and maybe not catch the idea really well. I have a basic question. What’s the benefit of using the virtual sequence? We can do pretty much do the same thing in the test, right? Is it just to group the sequences? Thanks, Cate

   Reply

   1. There are a couple of benefits using the virtual sequence over doing the same in a test.

      • It is easier to reuse. You can reuse the virtual sequence used in the module level to the full-chip level, for example. If you coordinate the sequences in a test, you will need to modify the test because it is tightly coupled with the component hierarchy.
      • You can easily create hierarchical sequences if you need to do so in the future.

      Reply

8. Hi Keisuke san,

   I tried to read more the the sequencer arbitration, but I couldn’t find anything that can explain clearly to me how the SEQ_ARB_FIFO, SEQ_ARB_RANDOM work. Can you give an example to illustrate.

   For example, when I forked

   fork 
       begin repeat(2)
         #1;
         seqA.start(m_sqr, this, 500);
        end
        begin repeat(2)
         #2;
         seqA.start(m_sqr, this, 500);
        end
        begin repeat(2)
         #3;
         seqA.start(m_sqr, this, 200);
        end
   join
   

   I know that start will not return until seq’s body is completed. Let’s say it takes 10 time unit.

   I can see the seq thread should be
   @1 seqA
   @2 seqA, seqB
   @3 seqC
   @11 seqA finished. Then it is the only one that can request again. I can’t figure it out.

   Many thanks.

   Loren

   Reply

   1. Sorry for the slow response. I have written a new article about Sequence Arbitration. I hope it helps.

      Reply

9. Hi Keisuke San,

   Can you explain how to parameterize a uvm_sequence_item? For example, I have a interface, and I want to have the address and data width parametrizable.

   I think I can write the base class like.

   class bus_item#( ADDR_WIDTH = 8, DATA_WIDTH=8) extends uvm_sequence_item
   `uvm_object_utils( bus_item#(ADDR_WIDTH, DATA_WIDTH))
   …

   So when I create a derive class. Should it be?
   class d_bus_item extends bus_item#(ADDR_WIDTH, DATA_WIDTH)
   `uvm_object_utils( d_bus_item)

   Also when I use the class my_seq extends uvm_sequence#(packet), is the packet the parameter in uvm_sequence?

   These are my confusion.
   1. I am not sure where to place the parameter in the derived class. For example, `uvm_object_utils( d_bus_item#(ADDR_WIDTH, DATA_WIDTH)).
   2. If my base class is not parameterized, can I derived a class and parameterize it?

   Many thanks.

   Reply

   1. A parameterized class needs to be specialized (meaning you need to specify the parameter values) before use. Your code won’t compile because the ADDR_WIDTH and the DATA_WIDTH are not specified.

      // This won't compile because ADDR_WIDTH and DATA_WIDTH are not specified. class d_bus_item extends bus_item#( ADDR_WIDTH, DATA_WIDTH );

      // This won't compile because ADDR_WIDTH and DATA_WIDTH are not specified. class d_bus_item extends bus_item#( ADDR_WIDTH, DATA_WIDTH );

      

      You can either make the d_bus_item parameterized:

      // make d_bus_item parameterized, too class d_bus_item#( ADDR_WIDTH, DATA_WIDTH ) extends bus_item#( ADDR_WIDTH, DATA_WIDTH ); `uvm_object_param_utils( d_bus_item #( ADDR_WIDTH, DATA_WIDTH ) ) // make sure to use "param_utils"

      // make d_bus_item parameterized, too class d_bus_item#( ADDR_WIDTH, DATA_WIDTH ) extends bus_item#( ADDR_WIDTH, DATA_WIDTH ); `uvm_object_param_utils( d_bus_item #( ADDR_WIDTH, DATA_WIDTH ) ) // make sure to use "param_utils"

      

      and specialize the d_bus_item when you instantiate it:

      d_bus_item#( 8, 8 ) d;

      d_bus_item#( 8, 8 ) d;

      Or, specialize the bus_item:

      // d_bus_item is no longer a parameterized class class d_bus_item extends bus_item#( 8, 8 ); `uvm_object_utils( d_bus_item )

      // d_bus_item is no longer a parameterized class class d_bus_item extends bus_item#( 8, 8 ); `uvm_object_utils( d_bus_item )

      

      Since the bus_item class has the default parameter values, you can also write:

      class d_bus_item extends bus_item; // < -- same as writing bus_item#( 8, 8 )

      class d_bus_item extends bus_item; // < -- same as writing bus_item#( 8, 8 )

      Similarly, when you did:

      class my_seq extends uvm_sequence#( packet );

      class my_seq extends uvm_sequence#( packet );

      you specialized the uvm_sequence class with the packet type.

      You can add new parameters to the derived class, too.
      

      Reply

10. Thanks Keisuke san. You explained the usage very well.

    If I understand it correctly, can I summarize it this way?
    For a derived class also can change the parameters, I need to declare it this way.
    class A_item#(int a) extends B_item#(int a)
    `uvm_object_param_utils(A_item#(int a)) <– I used the param_utils, and I included the param.

    If my drived class will use a fixed parameter like 8, I need declare it this way.
    class A_item extends B_item#(8) <– I used the fix parameter
    `uvm_object_utils(A_item) <– this is not parameterized class

    Many thanks.

    Loren

    Reply

    1. You are right.

       Reply

       1. Hi shimizu,
          In some pdfs like uvm_user_guide, i have seen people using virtual sequences contain only sub-sequences and virtual sequencers contain the subsequencers
          In the env, they set the virtual_sequecer.sub_seqr = agent.sequencer

          Then in test, they define the default_sequence of the virtual sequencer to be the virtual sequence using config_db

          Here you keep the sequencers in virtual sequence

          Which approach you would suggest

          Thanks
          Sasi

          Reply

          1. I would suggest not to use a virtual sequencer as it is not needed. Please see my old comment.

             Reply

             1. Hi, I am just eager how a sequence will be run if sequencer handle is not passed.
                Say, if vir_seq.start(null) is called , please explain how does it start() method works.

             2. Basically the start method executes the body task of the vir_seq, but no sequencer is involved when the sequencer argument is null.

11. How I set a value to variable in the sequence, when i start the sequence with `uvm_do_* macro? Because I don’t need to create the sequence when I use uvm_do. I tried setting the variable as rand type and tried to use uvm_do_with, but it doesn’t work.

    Reply

    1. If you could paste how did you call the `uvm_do_with, I might be able to help.

       Reply

       1. Thanks, I was able to make it work with `uvm_do_with. But my requirement is that I don’t want to set the variable always, but only on certain occasions. Making it as rand type randomizes it always(even when I just use `uvm_do).

          Reply

          1. How about disabling random variables with rand_mode like your_variable.rand_mode(0)?

             Reply

12. HI KEISUKE,

    1) I recently came across an interview question regarding Virtual sequencer.I know the application of virtual sequencer.

    Interview Question : What is virtual sequencer? Is it possible to drive two different sequences with out using virtual sequences/sequencers on different agents?

    – If Yes,Then what is the purpose of virtual sequences/sequencers?
    – If No,what makes the advantage using it.

    can you let me know with some scenario ?

    -Raja.

    Reply

    1. You can start sequences on multiple sequencers without using a virtual sequence. But if you do, you can extend it, reuse it, and create hierarchical sequences with it.

       Reply

13. Hello Shimizu-san,

    Thank you very for your great tutorial.
    I have a question: can we start a virtual sequence in another virtual sequence (like in no3 I see sequence of sequences by using m_sequencer ). Can we do similar things with two (or more) virtual sequences. If possible could you please recommend the way ?

    Thank you.

    Reply

    1. Yes, you can. This is a virtual sequence (gift_boxed_jelly_beans_virtual_sequence) that runs another virtual sequence (jelly_bean_recipe_virtual_sequence).

       class gift_boxed_jelly_beans_virtual_sequence extends uvm_sequence; `uvm_object_utils( gift_boxed_jelly_beans_virtual_sequence )   rand int unsigned num_jelly_bean_flavors; // knob jelly_bean_recipe_virtual_sequence jb_seq;   constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors inside { [2:3] }; }   function new( string name = "" ); super.new( name ); jb_seq = jelly_bean_recipe_virtual_sequence::type_id::create( .name( "jb_seq" ), .contxt( get_full_name() ) ); endfunction: new   task body(); repeat ( num_jelly_bean_flavors ) begin assert( jb_seq.randomize() ); jb_seq.start( .sequencer( null ) ); // start another virtual sequence end endtask: body endclass: gift_boxed_jelly_beans_virtual_sequence

       class gift_boxed_jelly_beans_virtual_sequence extends uvm_sequence; `uvm_object_utils( gift_boxed_jelly_beans_virtual_sequence ) rand int unsigned num_jelly_bean_flavors; // knob jelly_bean_recipe_virtual_sequence jb_seq; constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors inside { [2:3] }; } function new( string name = "" ); super.new( name ); jb_seq = jelly_bean_recipe_virtual_sequence::type_id::create( .name( "jb_seq" ), .contxt( get_full_name() ) ); endfunction: new task body(); repeat ( num_jelly_bean_flavors ) begin assert( jb_seq.randomize() ); jb_seq.start( .sequencer( null ) ); // start another virtual sequence end endtask: body endclass: gift_boxed_jelly_beans_virtual_sequence

       And this is a test that runs the above virtual sequence.

       class jelly_bean_recipe_test extends jelly_bean_base_test; `uvm_component_utils( jelly_bean_recipe_test )   function new( string name, uvm_component parent ); super.new( name, parent ); endfunction: new   task main_phase( uvm_phase phase ); gift_boxed_jelly_beans_virtual_sequence jb_vseq;   phase.raise_objection( .obj( this ) ); jb_vseq = gift_boxed_jelly_beans_virtual_sequence::type_id::create( .name( "jb_vseq" ) ); jb_vseq.jb_seq.jb_seqr1 = jb_env.jb_agent1.jb_seqr; jb_vseq.jb_seq.jb_seqr2 = jb_env.jb_agent2.jb_seqr; assert( jb_vseq.randomize() ); jb_vseq.start( .sequencer( null ) ); // start the virtual sequence #100ns ; phase.drop_objection( .obj( this ) ); endtask: main_phase endclass: jelly_bean_recipe_test

       class jelly_bean_recipe_test extends jelly_bean_base_test; `uvm_component_utils( jelly_bean_recipe_test ) function new( string name, uvm_component parent ); super.new( name, parent ); endfunction: new task main_phase( uvm_phase phase ); gift_boxed_jelly_beans_virtual_sequence jb_vseq; phase.raise_objection( .obj( this ) ); jb_vseq = gift_boxed_jelly_beans_virtual_sequence::type_id::create( .name( "jb_vseq" ) ); jb_vseq.jb_seq.jb_seqr1 = jb_env.jb_agent1.jb_seqr; jb_vseq.jb_seq.jb_seqr2 = jb_env.jb_agent2.jb_seqr; assert( jb_vseq.randomize() ); jb_vseq.start( .sequencer( null ) ); // start the virtual sequence #100ns ; phase.drop_objection( .obj( this ) ); endtask: main_phase endclass: jelly_bean_recipe_test

       Reply

       1. Dear Shimizu-san,

          Thank you very much for your help. It works well.

          Reply

          1. You are welcome.

             Reply

             1. Hi, If I create a virtual_seq with only one sequence and start this virtual_seq in my test with actual sequencer (instead of null), then will that be considered as normal sequence? If yes, then only way simulator knows it is a virtual sequence is by the way start is called?

             2. I would say your sequence is a non-virtual sequence, not because you started the sequence on a (non-null) sequencer, but because it is a sequence of another sequence.

                You can start a virtual sequence on a (non-null) sequencer. For example, the virtual sequence can send sequence items to the sequencer while it starts other sequences on their sequencers. My definition of virtual sequence is that it starts sub-sequences on multiple sequencers.

       2. Hi Keisuke,

          Can we run a sequence on multiple sequencers in parallel, can you please explain.

          Reply

          1. You cannot start the same sequence on multiple sequencers in parallel unless you clone it because the sequence keeps track of its sequence state (once a sequence is started, it cannot be started again until it is finished or stopped).

             Reply

14. hi Mr. Shimizu,

    virtual sequencer and physical sequencer exit from main phase prematurely before test completes. have you seen this? if so, how to resolve it? Thank you.

    Ed

    Reply

    1. Sorry for the very slow reply. It’s most likely objections are dropped prematurely. You could use +UVM_OBJECTION_TRACE command-line argument to trace objection activity.

       Reply

15. Hi Keisuke: The definition of your “same_flavored_jelly_beans_sequence” class does not have a member called “flavor”. How were you able to assign some values inside your “jelly_bean_recipe_virtual_sequence” class for the “jb_seq1” and “jb_seq2” sequences?

    Reply

    1. Actually, I slightly modified the original same_flavored_jelly_beans_sequence to have the flavor property for this tutorial. Sorry for the confusion.

       class same_flavored_jelly_beans_sequence extends uvm_sequence#( jelly_bean_transaction );   // knobs   rand int unsigned num_jelly_beans; rand jelly_bean_transaction::flavor_e flavor;  local same_flavored_jelly_beans_sequence self = this;   constraint num_jelly_beans_con { num_jelly_beans inside { [1:4] }; }   function new( string name = "" ); super.new( name ); endfunction: new   task body(); jelly_bean_transaction jb_tx; repeat ( num_jelly_beans ) begin jb_tx = jelly_bean_transaction::type_id::create( .name( "jb_tx" ) ); start_item( jb_tx ); assert( jb_tx.randomize() with { this.flavor == self.flavor; } ); `uvm_info( get_name(), { "n", jb_tx.sprint() }, UVM_LOW ) finish_item( jb_tx ); end endtask: body   `uvm_object_utils_begin( same_flavored_jelly_beans_sequence ) `uvm_field_int ( num_jelly_beans, UVM_ALL_ON ) `uvm_field_enum( jelly_bean_transaction::flavor_e, flavor, UVM_ALL_ON ) `uvm_object_utils_end endclass: same_flavored_jelly_beans_sequence

       class same_flavored_jelly_beans_sequence extends uvm_sequence#( jelly_bean_transaction ); // knobs rand int unsigned num_jelly_beans; rand jelly_bean_transaction::flavor_e flavor; local same_flavored_jelly_beans_sequence self = this; constraint num_jelly_beans_con { num_jelly_beans inside { [1:4] }; } function new( string name = "" ); super.new( name ); endfunction: new task body(); jelly_bean_transaction jb_tx; repeat ( num_jelly_beans ) begin jb_tx = jelly_bean_transaction::type_id::create( .name( "jb_tx" ) ); start_item( jb_tx ); assert( jb_tx.randomize() with { this.flavor == self.flavor; } ); `uvm_info( get_name(), { "n", jb_tx.sprint() }, UVM_LOW ) finish_item( jb_tx ); end endtask: body `uvm_object_utils_begin( same_flavored_jelly_beans_sequence ) `uvm_field_int ( num_jelly_beans, UVM_ALL_ON ) `uvm_field_enum( jelly_bean_transaction::flavor_e, flavor, UVM_ALL_ON ) `uvm_object_utils_end endclass: same_flavored_jelly_beans_sequence

       Reply

       1. Hi Keisuke,
          What’s the difference between “this” and “self” in the line jb_tx.randomize() with {} above.

          Thanks a lot for this great tutorial. Really learned a lot.
          Hulin

          Reply

          1. In the line below:

             assert( jb_tx.randomize() with { this.flavor == self.flavor; } );

             assert( jb_tx.randomize() with { this.flavor == self.flavor; } );

             this refers to the jb_tx object (not the current instance of same_flavored_jelly_beans_sequence), whereas self refers to the current instance of same_flavored_jelly_beans_sequence.

             Reply

16. Hi Keisuke,

    /////////////////////
    In the virtual sequence, we do not create sequencer, but create sequence. jb_seq1, jb_seq2.
    //////////////////

    class jelly_bean_recipe_virtual_sequence extends uvm_sequence#( uvm_sequence_item );
      ...
       jelly_bean_sequencer jb_seqr1;
       jelly_bean_sequencer jb_seqr2;
     
       same_flavored_jelly_beans_sequence jb_seq1;
       same_flavored_jelly_beans_sequence jb_seq2;
     
       function new( string name = "" );
          super.new( name );
       endfunction: new
     
       task body();
          jb_seq1 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq1" ), .contxt( get_full_name() ) );
          jb_seq2 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq2" ), .contxt( get_full_name() ) );
    ....
    

    //////////////////////
    In the test, we create the virtual sequence jb_vseq.
    //////////////////////

          jb_vseq = jelly_bean_recipe_virtual_sequence::type_id::create( .name( "jb_vseq" ), .contxt( get_full_name() ) );
          jb_vseq.jb_seqr1 = jb_env.jb_agent1.jb_seqr;
          jb_vseq.jb_seqr2 = jb_env.jb_agent2.jb_seqr;
          assert( jb_vseq.randomize() );
          jb_vseq.start( .sequencer( null ) );
    

    I have some questions here

    1. When should we do create? From the code, it seems like we do not need to create sequencer. My understanding is that we do not need to do type override for sequencer so that we do not need to create it in the sequence? Please correct me.

    2. In the test, I think it only pass the handle of jb_env.jb_agent1.jb_seqr to jb_vseq.jb_seqr1? Am i correct? When could we just pass the handle?

          jb_vseq.jb_seqr1 = jb_env.jb_agent1.jb_seqr;
          jb_vseq.jb_seqr2 = jb_env.jb_agent2.jb_seqr;
    

    3. if we have, for example, 4 sequences in one virtual sequence: vseq , if we want to set the default sequence, we could use virtual sequencer in the test to control it together. Is that one of the usage for virtual sequencer? If we do not have virtual sequencer and the sequencer for virtual sequence is null
    (jb_vseq.start( .sequencer( null )) , does that mean we need to set default sequence one by one in the virtual sequence. Or for virtual sequence we should only do .start, but not default sequence to start a sequence.

     uvm_config_db#(uvm_object_wrapper)::set(this,  
                                                  "env.vsqr.main_phase",  
                                                  "default_sequence",  
                                                   vseq::type_id::get()); 
    

    Thank you very much

    Reply
    1. 1. You could use a virtual sequencer, but I did not do it in my article.
       2. Yes, these are object handle assignments.
       3. If you want to start a virtual sequence as the default sequence, you need to have a virtual sequencer.

       Reply

       1. Thanks Keisuke for your reply, I got it.

          Best,

          Reply

17. Hi Keisuke,

    For virtual sequence reused by different tests, should we put the virtual sequence in env? Is that a good way? Otherwise is there any better way to handle the virtual sequence?

    Thank you very much

    Best,

    Reply

    1. I would create a package for the virtual sequence and let the test import it.

       Reply

18. Hi KEISUKE,
    Will please explain the difference between import a package and include a file with a good example?

    Reply

    1. The `include is a compiler directive used to insert a file as if it is copy & pasted.

       jelly_bean_pkg::jelly_bean_transaction jb_xact; // note the "jelly_bean_pkg::"

       jelly_bean_pkg::jelly_bean_transaction jb_xact; // note the "jelly_bean_pkg::"

       On the other hand, the import declaration DOES NOT insert the contents of the package. It just provides direct visibility of identifiers within a package. For example, unless you import the package, you need to use the package name qualifier when you use the jelly_bean_transaction declared in the jelly_bean_pkg.

       import jelly_bean_pkg::*; // all identifiers in the package are "visible" in this scope   jelly_bean_transaction jb_xact; // no package qualifier is needed

       import jelly_bean_pkg::*; // all identifiers in the package are "visible" in this scope jelly_bean_transaction jb_xact; // no package qualifier is needed

       With the import declaration, you can use the jelly_bean_transaction without the package name qualifier.

       import jelly_bean_pkg::*; // all identifiers in the package are "visible" in this scope   jelly_bean_transaction jb_xact; // no package qualifier is needed

       import jelly_bean_pkg::*; // all identifiers in the package are "visible" in this scope jelly_bean_transaction jb_xact; // no package qualifier is needed

       Reply

19. I have written an env with 3 agents like apb agent and 2 other agents.
    For this,I have used virtual sequencer using m_sequencer method.(normal uvm_sequencer which holds the handles to different sequences. )

    When it calls UVM_TEST= test_name from command line ,All pre-run phases are working absolutely correct.But it is stuck at run phase.
    It is stuck at below :
    m_vseq.start(v_seqr.apb_seqr);
    It is not going ahead.
    Can somebody help me to solve this?

    Reply

    1. Check the body task of m_vseq and the body task of the sequences that m_vseq starts. Is m_vseq a virtual sequence? Then, do you want to start it on apb_seqr?

       Reply