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ClueLogic > Archive for SystemVerilog

Category: SystemVerilog

Hidden Gems of SystemVerilog – 4. Solving Sudoku with Uniqueness Constraints

January 29, 2017July 2, 2017 Keisuke Shimizu

Last Updated on July 2, 2017 This is a sequel to my old article about solving Sudoku. Last time, someone asked a question about using the “unique” constraint to solve Sudoku. The “unique” constraint, which was added to IEEE Std Read More …

SystemVerilogconstraint, randomize, Sudoku, unique2 Comments

UVM Tutorial for Candy Lovers – 25. Using a C-Model

February 21, 2015 Keisuke Shimizu

We often use a C-model as a reference model. Thanks to the direct programming interface (DPI) of SystemVerilog, using C-model has never been easier. We will show you how to use a C-model in our jelly bean scoreboard. Original Scoreboard Read More …

SystemVerilog, UVMDPI-C, uvm_subscriber5 Comments

Hidden Gems of SystemVerilog – 3. Solving Sudoku

February 3, 2015March 5, 2016 Keisuke Shimizu

A few people (Chris Drake, Tudor Timi, and anilraj) have already solved Sudoku using SystemVerilog. So, I am not the first one, but I can’t resist doing it because it sounds a lot of fun! I tried not to look Read More …

SystemVerilogconstraint, randomize, Sudoku7 Comments

Hidden Gems of SystemVerilog – 2. Name spaces

November 1, 2014December 27, 2015 Keisuke Shimizu

Yesterday was Halloween and candies are around every corner, even in my code. But do you think it compiles? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 `define candy   function void candy; Read More …

SystemVerilogname space11 Comments

Hidden Gems of SystemVerilog – 1. Compilation unit scope

October 26, 2014December 27, 2015 Keisuke Shimizu

This is a new series of technical blogs that focus on SystemVerilog itself. This is not a SystemVerilog tutorial, but rather I would like to dig into the SystemVerilog language and show you the features that not many people may Read More …

SystemVerilog$unit, compilation unit2 Comments
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