Last Updated: September 11, 2013 A UVM driver and a UVM sequencer are connected using a UVM sequence item port and an export. This post will explain how the sequence item port works.
Author: Keisuke Shimizu
Verification expert with exceptional understanding of SystemVerilog and UVM/VMM as a result of more than 13 years of experience in the design verification field.
Specializes in providing highly reusable constrained-random verification architecture and implementation to uncover hard-to-find design bugs, with a focus on coverage metrics. Passion for pursuing new verification technology: an early adopter of VMM (2006). Experience with a wide-range of verification targets from PHY to a reconfigurable array processor. Author of technical blog series "UVM Tutorial for Candy Lovers." Creator of an open-source SystemVerilog generic library to share deep verification knowledge.
UVM Tutorial for Candy Lovers – 10. Inside Candy Factory
Last Updated: September 9, 2013 UVM factory is used to create UVM objects and components. This post will explain the UVM factory using jelly beans (as you expected) and reveal what happens behind the scenes in the factory.
UVM Tutorial for Candy Lovers – 9. Register Abstraction
Last Updated on November 6, 2016 This post will explain how to use the UVM Register Abstraction Layer (RAL) to generate register transactions.
UVM Tutorial for Candy Lovers – 8. Configurations
Last Updated: April 4, 2014 This post will give an explanation on UVM configuration objects, since the earlier posts did not cover much on them.
UVM Tutorial for Candy Lovers – 7. Virtual Sequence
Last Updated: March 26, 2016 (added the link to EDA Playground) Did you know the mix of two lemon and two coconut jelly beans will create the flavor of lemon meringue pie? And the mix of two strawberry and two Read More …
UVM Tutorial for Candy Lovers – 6. Tasting
Last Updated: September 1, 2014 The anticipated culmination of the UVM for Candy Lovers series is revealed in this post. Using the created verification components and writing out a test class, the actual simulation is prepared to run.
UVM Tutorial for Candy Lovers – 5. Environment
Last Updated: April 4, 2014 This post will provide a continued explanation on the rest of the verification components.
UVM Tutorial for Candy Lovers – 4. Agent
Last Updated: July 12, 2015 The last post concentrated on the transactions and sequences of the jelly-bean taster system. This post will explain the verification components in the verification environment further in depth.
UVM Tutorial for Candy Lovers – 3. Transactions and Sequences
Last Updated: June 29, 2014 This post will provide an explanation on the SystemVerilog code itself. Please see Recipe for the class diagram.
UVM Tutorial for Candy Lovers – 2. Recipe
Last Updated: April 4, 2014 While the last post clarified the verification components of the jelly-bean taster, this post will provide a focus for the jelly-bean recipe.