UVM Tutorial for Candy Lovers – 1. Overview

Last Updated: April 4, 2014

Accellera’s recently released UVM may change the future of verification, as verification methodology seems to be consolidated in this UVM. This post will provide a simple tutorial on this new verification methodology. Rather than focusing on AXI, OCP, or other system buses in existence, this tutorial will be based on the hypothetical example of a jelly-bean generator. The test bench will generate many jelly-bean flavors in a constrained random manner and the system will evaluate palatable flavors. This does not require the knowledge of any system bus.

The verification components used in the process will be described below.

Verification components
Verification Components

The left figure shows the relationship of the verification components. The jelly_bean_taster is the design-under-test (DUT) module.

The jelly_bean_sequencer will create jelly-bean recipes and send them to the jelly_bean_driver. From the information provided in the recipe, the driver creates jelly beans. The driver passes the jelly beans through the jelly-bean interface (jelly_bean_if) to the jelly_bean_taster, which will check the jelly-bean taste.

Concurrently, as the jelly beans are being created, the jelly_bean_monitor will capture the flavor and color of the recently produced. This information will be passed down to the jelly-bean functional coverage subscriber, referred to as the jelly_bean_fc_subscriber. The subscriber records and totals the jelly beans based on their color and flavor.

The jelly_bean_scoreboard is a component that checks if the jelly_bean_taster is responding correctly. The scoreboard subscribes the information from the jelly_bean_monitor.

Jelly-Bean Components
Class Diagram of Verification Components

The second figure shows the verification components in a class diagram. The light blue boxes refer to the classes in the UVM basic class library, while the darker boxes indicate the classes created in this tutorial.

Though the post ends here, the next will show the structure of the jelly-bean recipes.

Get source code

21 thoughts on “UVM Tutorial for Candy Lovers – 1. Overview”

  1. I use Synopsys vcs to run jb1.sv, get this error at simulation

    UVM_FATAL @ 0: reporter [NOCOMP] No components instantiated. You must either instantiate at least one component before calling run_test or use run_test to do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name in the argument to run_test(). Exiting simulation.

    then I run jb2.sv, and got this error

    Error-[TMAFTC] Too many arguments to function/task call
    /home/ichris/Desktop/project/uvm-1.1a/src/base/uvm_registry.svh, 197
      The above function/task call is done with more arguments than needed.
    Error-[TMAFTC] Too many arguments to function/task call
    jb2.sv, 285
      The above function/task call is done with more arguments than needed.

    what is wrong in both cases???

    1. Hello,

      For the jb1.sv to work, you must use +UVM_TESTNAME=jelly_bean_test option when you run VCS.

      I had a bug in jb2.sv. I forgot to code the new() function of the jelly_bean_recipe_virtual_sequence class. I have already fixed the bug, and the new code is ready to download. Thank you for pointing out the bug.

  2. Hi Keisuke,

    I am set to verify a RTL model based on C-Golden Ref.Model. Here I would like to write into the UVM registers all the required configurations and pass the same to C & RTL. And I am familiar with UVM registers configurations and DPI calls from SV to C.

    But, I am not sure how to implement the DPI’s in UVM.
    1) How/where do we add DPI calls and C-functions in the test so that the C-Code runs at first and then dumps the values to some dynamic arrays and later, I access them to compare the results with RTL in the scoreoard ?

    Can you please add some example to this. It would be some immense help

    Thank You in Advance..!

    1. Hi Surya,

      I am not sure if I understand your question correctly, but you can call your C-functions from the main_phase of your test to generate expected values. As you mentioned, you can store the expected values in a dynamic array and use them later in the scoreboard. Did I answer your question?

  3. Hi Keisuke,

    Appreciate your work done on this site – makes UVM world more clear and easy to understand.

    Just one question: do you have this UVM tutorial (each lesson) in other formats (presentations – ppt, with sound and everything)?
    Maybe somewhere on youtube? It will be interesting to have access to each lesson in a presentation format to listen as a class …

    Thank you.

  4. Thank you for this tutorial, Keisuke.
    I assume, the makefile was written for Linux. I use questasim and run it on Windows 7. Can you tell me, how should i modify this makefile and what do i have to do to execute it?

      1. Tuyen, it’s Questasim 10.0b. I ‘ve tried to write a do-file with a following code:
        vsim work.top +UVM_TESTNAME = jelly_bean_test
        seems like it works fine, but i still don’t know how to adopt lines
        ifeq “$(TUTORIAL)” “1”
        tutorial_file := tutorial_1_to_6.sv
        testname := jelly_bean_test
        and so on.
        I’ll be very grateful, if you tell me, how to do it

        1. Dear Borya,
          What operating system do you run questasim.

          If you run in linux you just run follow command:”make questa TUTORIAL=6″
          I had try it, it work well. If you have any concern, please let me know.

  5. Hi Keisuke Shimizu,

    Appreciate your work with this blog.

    I observed in your source on using “uvm_resource_db”.
    But, we use “uvm_config_db”. Can you please elaborate
    the pros and cons of both. And, the recommended one.

    = Murugesan

    1. A general rule of thumb is that you should use uvm_config_db if a hierarchical context is important, otherwise uvm_resource_db should be used. For example, the set function of uvm_config_db takes a uvm_component as the first argument to facilitate the specification of the hierarchical context.

      static function void uvm_config_db#(T)::set( uvm_component cntxt,
                                                   string        inst_name,
                                                   string        field_name,
                                                   T             value );

      whereas the set function of uvm_resource_db doesn’t:

      static function void uvm_resource_db#(T)::set( string     scope, // any string
                                                     string     name,
                                                     T          val,
                                                     uvm_object accessor = null );

      Having said that, we used uvm_resource_db in our tutorial. We should have used uvm_config_db instead.

      1. Keisuke,

        I struggle a long time about the UVM compilation. Would you please share me some clue about debug the errors as follows? I had add the

        I think we do not need to do typedef for clk_trans, right?


        clk_trans trans = clk_trans::type_id::create("trans");
        ncvlog: *E,SVNOTY (/export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/tb/agent/clk_agent/clk_seq_lib.sv,27|16): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.

        Here is the lines I try to do the setting of UVM, I also add import uvm_pkg::*; and include “uvm_macros.svh” at the top of all the files.

        -uvmhome /export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/lib/uvm-1.1 \ 
        -sv /export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/lib/uvm-1.1/src/dpi/uvm_dpi.cc /export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/lib/uvm-1.1/src/uvm.sv /export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/tb/top/top.sv \
        +UVM_TESTNAME=ovprj_base_test \
        /export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/lib/uvm-1.1/src/uvm_pkg.sv \
        +incdir+/export/home/basin/kevin.chen/prj/ov9281_uvm/frontend/uvm/lib/uvm-1.1/src \
          1. Hi Keisuke,

            Yes, i got the root cause of it. There is a typo for the ifdef. Would you please tell me is there any reason why we use this piece of code?

            `ifndef clk_trans
            `define clk_trans

            Thank you very much


  6. Hi Keisuke,
    I am getting the following error when running on vcs.. please help me to resolve this

    make[1]: *** [product_timestamp] Error 1
    make[1]: Leaving directory `uvm-tutorial-for-candy-lovers-master/run/csrc’
    Make exited with status 2

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