In the previous article, we explained how to filter messages using a verbosity threshold. This article explains how to send the messages to a file (or files). Message Example As an example, we added several message macros with different severity Read More …
Author: Keisuke Shimizu
Verification expert with exceptional understanding of SystemVerilog and UVM/VMM as a result of more than 13 years of experience in the design verification field.
Specializes in providing highly reusable constrained-random verification architecture and implementation to uncover hard-to-find design bugs, with a focus on coverage metrics. Passion for pursuing new verification technology: an early adopter of VMM (2006). Experience with a wide-range of verification targets from PHY to a reconfigurable array processor. Author of technical blog series "UVM Tutorial for Candy Lovers." Creator of an open-source SystemVerilog generic library to share deep verification knowledge.
UVM Tutorial for Candy Lovers – 27. Message Verbosity
UVM has a rich reporting facility. This article explains how to use a verbosity threshold to filter messages. Pre-defined Verbosity Levels UVM pre-defines six verbosity levels; UVM_NONE to UVM_DEBUG. These levels are nothing but integer enum values (the parentheses in Read More …
UVM Tutorial for Candy Lovers – 26. Sequence Arbitration
Our jelly-bean business has been doing so well that we started to receive multiple jelly-bean orders at the same time. Some customers requested expedited shipping, too. But how to prioritize the requests? It’s time to learn about sequence arbitration. Today’s Read More …
UVM Tutorial for Candy Lovers – 25. Using a C-Model
We often use a C-model as a reference model. Thanks to the direct programming interface (DPI) of SystemVerilog, using C-model has never been easier. We will show you how to use a C-model in our jelly bean scoreboard. Original Scoreboard Read More …
Hidden Gems of SystemVerilog – 3. Solving Sudoku
A few people (Chris Drake, Tudor Timi, and anilraj) have already solved Sudoku using SystemVerilog. So, I am not the first one, but I can’t resist doing it because it sounds a lot of fun! I tried not to look Read More …
Hidden Gems of SystemVerilog – 2. Name spaces
Yesterday was Halloween and candies are around every corner, even in my code. But do you think it compiles? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 `define candy function void candy; Read More …
Hidden Gems of SystemVerilog – 1. Compilation unit scope
This is a new series of technical blogs that focus on SystemVerilog itself. This is not a SystemVerilog tutorial, but rather I would like to dig into the SystemVerilog language and show you the features that not many people may Read More …
UVM Tutorial for Candy Lovers – 24. Register Access through the Back Door
Last Updated: February 14, 2015 (fixed broken EDA Playground link) This post will add back-door access to the registers defined in Register Abstraction. With a few additional lines of code, you can access the registers through the back door. DUT Read More …
UVM Tutorial for Candy Lovers – 23. Jelly Bean Taster in UVM 1.2
Last Updated: February 21, 2015 My first series of UVM tutorials (#1 to #6) was posted more than three years ago. Since then, UVM (and my knowledge about it) has evolved and I always wanted to update my articles and Read More …
UVM Tutorial for Candy Lovers – 22. Phasing
When we created the jelly_bean_driver in Agent, we coded the build_phase function and the run_phase task, but who actually calls them? The answer is uvm_phase class. UVM Phases UVM has nine common phase classes (shown in yellow) and twelve run-time Read More …